This is still an extremely demanding proposition. “Packaging is not as simple as saying, ‘I want to produce 100,000 wafers a month,’” says Jim McGregor, a longtime chip industry analyst and founder of Tirias Research, referring to the constant flow of chips through various stages of production. “It really depends on whether Intel [packaging] Factories can make trades. If we see them expanding this activity even more, it will be a signal to them.”
Last month, Anwar Ibrahim, the Prime Minister of Malaysia, revealed in a Facebook post that Intel was expanding its Malaysian chip production facilities, which were built in the 1970s. Ibrahim said Intel foundry chief Naga Chandrasekaran has “outlined plans to begin the first phase” of expansion, which will include advanced packaging.
“I welcome Intel’s decision to begin operations of the complex later this year,” reads a translated version of Ibrahim’s post. Intel spokesman John Hipsher confirmed it was building additional chip assembly and testing capabilities in Penang “amid growing global demand for Intel Foundry packaging solutions.”
Package store
According to Chandrasekaran, who acquired Intel Foundry’s operations in 2025 and spoke exclusively to WIRED while reporting on this story, the term “advanced packaging” itself did not exist a decade ago.
Chips have always required some type of integration of transistors and capacitors that control and store energy. For a long time, the semiconductor industry has focused on miniaturization, or reducing the size of components on chips. As the world began to demand more from its computers in 2010, chips began to become even denser with processing units, high-bandwidth memory, and all the necessary interconnection parts. Eventually, chipmakers began using a “system-in-a-package” or “package-on-package” approach, in which multiple components were stacked on top of each other to squeeze more power and memory from the same square footage. 2D stacking has given way to 3D stacking.
TSMC, the world’s leading semiconductor manufacturer, began offering customers packaging technologies such as CoWoS (chip on wafer on a substrate) and later SoIC (system on an integrated chip). Basically, it was assumed that TSMC would handle not only the front-end of chip production – the wafer part – but also the back-end, where all the chip technology would be packaged into one whole.
At this point, Intel handed over its chipmaking position to TSMC but continued to invest in packaging. In 2017, a process called EMIB, or embedded multi-die interconnect bridge, was introduced, which was unique in that it reduced the actual connections, or bridges, between the components of a chip package. In 2019, it introduced Foveros, an advanced stacking process. The company’s next packaging improvement was a bigger step: EMIB-T.
Announced last May, EMIB-T promises to improve energy efficiency and signal integrity between all chip components. One former Intel employee with direct knowledge of the company’s packaging efforts tells WIRED that Intel’s EMIB and EMIB-T technologies were designed to be a more “surgical” way of packaging chips than the approach used by TSMC. Like most chip improvements, this one is designed to be more energy proficient, save space, and ideally – in the long run – save customers money. The company says EMIB-T will be rolled out to factories this year.